This page exists to chronicle all of the insane hoops one has to jump through to get Vivado to behave.

To create a custom Board File:
[[ https://docs.amd.com/r/en-US/ug895-vivado-system-level-design-entry/Introduction?tocId=F6i4Whhu7YXEryUAukRhtg]]

Adding board files [[https://support.xilinx.com/s/article/72033?language=en_US]]

Some intermediate-advanced level Verilog info:
[[https://zipcpu.com/]]

Examples of many common use cases in Verilog
[[http://fpgacpu.ca/fpga/index.html]]

Sometimes, you'll need to configure system variables to do... things?  I'm not clear on when this matters.  Anyways, the appropriate command is ''source <path to Xilinx installation directory>/Xilinx/Vivado/2020.1/settings64.sh''

<div figure wide>
|  {{:phylabs:lab_courses:phys-226-wiki-home:fpgas:arm_memory.png|}}  |
| Memory map for cortex-m4 style devices.  Mostly helpful to have in the background.   |
</div>

==== TCL ===
useful for a lot of automation, more common among pros than GUI for design.

**SPACES IN PATH NAMES ARE VERBOTEN! THEY CAUSE NOTHING BUT PAIN!**

[[https://docs.amd.com/r/en-US/ug835-vivado-tcl-commands/Tcl-Commands-Listed-by-Category]]

[[https://docs.amd.com/r/en-US/ug896-vivado-ip/Tcl-Commands-for-Common-IP-Operations?tocId=E4YoWK95_0eghocguA0MqQ]]

[[https://projectf.io/posts/vivado-tcl-build-script/]]

==== Lingo ===

  * RTL - [[https://en.wikipedia.org/wiki/Register-transfer_level|Register Transfer Level]].  Models a circuit in terms of digital signals between hardware registers and logical operations performed on signals.
    * RTL Attributes - Keywords for finer control.  Things like telling it how to infer memory or mark for debugging.
    * e.g. ''(* mark_debug = "TRUE" *)'' tags a register / wire to follow later.
  * TCL - Tool Command Line.  Scripting language often used with FPGAs.  Pronounced as letters or "tickle."
  * DSP - [[https://en.wikipedia.org/wiki/Digital_signal_processor | Digital Signal Processing]].  The process of manipulating incoming signals with digital circuitry, such as doing Fourier transforms, filtering, etc.
  * [[https://en.wikipedia.org/wiki/Microcontroller | Microcontroller]] - A complete computer in a single chip.  Implies CPU, memory, io, and so forth.
  * [[https://en.wikipedia.org/wiki/Microprocessor| Microprocessor]] - Just a CPU or other data manipulation hardware in a chip.
  * [[https://en.wikipedia.org/wiki/Embedded_system  | Embedded system]] - A computer system that is part of a larger device.  Think chips used in phones, cars, appliances, etc.
  * Verilog Datatypes
    * ''wire'' - an interconnect between devices.  Cannot store data, must be assigned a value by something
    * ''reg'' - A register, can store data freely.  Cannot directly be used as an output port, for that you need to ''assign'' a wire to the value of the register and use that.  
    * ''logic'' - similar to register.  However, if you try to assign it multiple values it just takes the latest one; registers are unpredictable and the output is ''X'' - unknown
  * ''.XDC'' - Xilinx Design Constraints file.  Defines input/output pins and such.  One for Red Pitaya is [[https://github.com/pavel-demin/red-pitaya-notes/blob/master/cfg/ports.xdc|here]].
  * ''IOB'' - Input Output Buffers
  * ''ARM'' -  Advanced RISC Machine
  * ''RISC'' - Reduced Instruction Set Computer
  * ''CISC'' -  Complex Instruction Set Computer
    * Basic difference is that CISC devices have some more specialized (but less used) commands so they can do some things in fewer clock cycles.  Downside is you have to know the commands.  Most modern PCs RISC based.
  * ''MGT''  Multi-Gigabit Transceiver.  High speed IO.
  * ''BUFG'' - Global buffer.  Near center of chip, particularly useful for high performance.
  * ''Fabric'' - Internal elements of the FPGA.  Usually just the logic blocks, interconnects, and IOs.
  * ''LVDS'' - Low Voltage Differential Signal.  Uses 2 pins for 1 bit of signal for better integrity.
  * ''PS'' - Processing System.  Traditional computer processor.
  * ''PL'' - Programmable Logic.  What you normally think of as the FPGA parts.
  * ''HDL'' - Hardware description language.  Basically VHDL and Verilog.
  * ''BEL'' - Basic Element of Logic.
  * ''DRC'' - Design Rule Check.  Check for sketchy shit.
  * ''SSN'' - Simultaneous Switching Noise.  How much noise you're liable to pick up from nearby pins.
  * ''UART'' - Universal Asynchronous Receiver/Transmitter.  Common communication protocol.  
    * Packets are:
      * 1 start bit 
        * always 0
      * 5-8 data bits
      * parity bit = SUM(data)%2
      * 1 or 2 stop bits
        * always 1
     * Usually sample midway though bit transmission for reliability
   * ''MMCM'' - Mixed Mode Clock Module.  Lets you create clocks & set phases.
   * ''CMT'' - Clock Management Tile
   * ''SPI'' - Serial Peripheral Interface.  Common communication protocol.
   * ''AXI'' - Advanced Extensible Interface
   * ''AMBA'' - Advanced Microcontroller Bus Architecture.  AXI is subset of this.
   * ''XML'' - eXtensible Markup Language.  Created by the SPIRIT Consortium standards organization.  Hence why you may see "spirit" in the files a lot.  Not haunted.
   * ''CDMA'' - Central Direct Memory Access
   * ''SG'' - Scatter Gather.  Refers to being able to address non-consecutive addresses simultaneously.  Often used for faster vector math.
   * ''HP'' - High Performance.  Counterpart to General Purpose.  Relevant for interconnects (AXI) that need to be fast.
   * ''0x'' - Indicates that following number is in he''x''adecimal.
   * ''CIC'' - Cascaded Integrator Comb.  Flavor of low-pass filter?  The integrators average things, like you'd expect, and the comb parts add a time-delayed version of the signal to itself (A-la CFD circuitry?).

==== AXI ====

Types of AXI interfaces:
  * Full - single address/data burst
    * 5 channels:
      * read addr
      * read data
      * write addr
      * write data
      * write response
  * Lite - single address / data, no burst.
    * Same channels, only 32 bit width transfer.
    * Need AXI_Interconnect to talk with AXI4 base
    * 1 signal gets you 1 response I think.
  * Streaming - Data only and burst transfer (fifo?)
    * Write only basically




[[https://digilent.com/blog/fpga-for-beginners-glossary-and-setup/]]

==== Misc links ====

[[https://projectf.io/posts/fpga-memory-types/]]

[[https://projectf.io/posts/fpga-sine-table/]]

Chinese site, but some useful info: [[https://leiblog.wang/static/FPGA/books/Vivado%E4%BB%8E%E6%AD%A4%E5%BC%80%E5%A7%8B/]]

[[http://ecen220wiki.groups.et.byu.net/00-tutorials/]]

[[http://ecen220wiki.groups.et.byu.net/resources/tool_resources/testbenches/]]

[[https://www.fpga4student.com/]] More Verilog, but still relevant.

[[https://opencores.org/]]

[[http://www.asic-world.com/verilog/veritut.html]]

[[https://www.rtlaudiolab.com/]] Specifically about processing audio

[[https://rajesh52.blogspot.com/?m=1 | VLSI interview questions]]

[[https://www.amd.com/en/corporate/university-program/workshops.html#tabs-78d8c6d64f-item-b7fdb37752-tab | AMD workshops]] - Slightly broken tutorials, but moderately better than nothing.