http://physlab-wiki.com/ 2026-05-07T04:15:22+00:00 http://physlab-wiki.com/ http://physlab-wiki.com/lib/tpl/UChicago/images/favicon.ico text/html 2022-05-19T16:39:51+00:00 Anonymous (anonymous@undisclosed.example.com) http://physlab-wiki.com/phylabs/lab_courses/phys-226-wiki-home/fpgas/pins?rev=1652992791&do=diff Here's a listing of the most relevant pins you may want to use Inputs Buttons: Name Pin Button 0 H2 Button 1 G3 Button 2 F1 Switches: Slide Switch 0 J6 Slide Switch 1 H5 Slide Switch 2 H6 Slide Switch 3 G4 Slide Switch 4 G5 Slide Switch 5 text/html 2025-06-17T14:08:25+00:00 Anonymous (anonymous@undisclosed.example.com) http://physlab-wiki.com/phylabs/lab_courses/phys-226-wiki-home/fpgas/ramanathan_tutorials?rev=1750183705&do=diff <https://www.digikey.it/it/maker/tutorials/2023/from-zero-to-verilog-hero-part-1-a-comprehensive-introduction> <https://www.digikey.it/it/maker/tutorials/2023/understanding-rtl-and-hdl-part-2-of-our-verilog-journey> <https://www.digikey.it/it/maker/tutorials/2024/understanding-the-chip-design-flow-part-3-of-our-verilog-journey> <https://www.digikey.it/it/maker/tutorials/2024/mastering-verilog-syntax-and-data-types-part-4-of-our-verilog-journey> <https://www.digikey.it/it/maker/tutorials/2024… text/html 2025-07-10T15:34:52+00:00 Anonymous (anonymous@undisclosed.example.com) http://physlab-wiki.com/phylabs/lab_courses/phys-226-wiki-home/fpgas/red-pitaya?rev=1752176092&do=diff This page is a collection of notes on the Red Pitaya platform The chip used is a xc7z010clg400-1 documentation hub <https://docs.amd.com/v/u/en-US/dh0050-zynq-7000-design-overview-hub> Official docs <https://docs.amd.com/v/u/en-US/ug865-Zynq-7000-Pkg-Pinout> Specific pinout info From a Slovenian university: <https://lniv.fe.uni-lj.si/redpitaya/index.html> Scottish EEE group wrote a whole book on the base FPGA <http://www.zynqbook.com/> Direct PDF link: text/html 2025-10-01T10:20:10+00:00 Anonymous (anonymous@undisclosed.example.com) http://physlab-wiki.com/phylabs/lab_courses/phys-226-wiki-home/fpgas/vivado?rev=1759328410&do=diff This page exists to chronicle all of the insane hoops one has to jump through to get Vivado to behave. To create a custom Board File: <https://docs.amd.com/r/en-US/ug895-vivado-system-level-design-entry/Introduction?tocId=F6i4Whhu7YXEryUAukRhtg> Adding board files <https://support.xilinx.com/s/article/72033?language=en_US> Some intermediate-advanced level Verilog info: <https://zipcpu.com/> Examples of many common use cases in Verilog